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Use the following steps to complete the wiring of the breadboard

  • Select your circuit. If this is your first time, choose the SR NAND or SR NOR.
  • Operate the switches in the circuit simulator. Read the description of the circuit if you need additional information.
  • Using the schematic, wire up the circuit in the breadboard simulator. When a wire end is placed in a socket of the breadboard that corresponds to a node on the schematic, the respective node of the schematic will turn red.
  • If a correct connection is made, the wire ends will snap into the socket.
  • Note that all the VCC (red wire) and GND (black wire) connections are already done.
  • When all the nodes are wired up, a red LED will light up near the VCC/GND terminals.
  • You may now operate the breadboard switches and observe the LED results.
  • When you wire up the circuit using a real digital trainer, do remember to wire the VCC and GND wires and power up the digital trainer.
  • You must login using your facebook account to save or restore the breadboard connections.
  • Click to close any of the panes (breadboard/schematic/description/help) and click on the corresponding menu item to open it.

If you are unfamiliar with the breadboard, there are many resources available online that explains how to they work.

SR NOR latch

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output 0s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values

    Notes:
  • Q0 is the previous state of Q and Q0 is the previous state of Q.
  • R and S are asynchronous inputs - that is the output responds to these input immediately. They are active high inputs. Click on their respective (SW7 and SW6) switches and observe.
  • S sets the output to 1 and R resets the output to 0.
  • Both R and S cannot be high at the same time - the output is undefined.